● Available Karachi, PK / Remote DV Engineer · 10xEngineers

Shahzaib
Kashif.

I design chips — and the tools that design chips.

Design Verification Engineer at 10xEngineers working on UCIe Protocol VIP. RISC-V International Advocate and CHERI Alliance Ambassador. I've taped out real silicon on Google's MPW6 shuttle, spoken at summits on three continents, and spent years building open hardware infrastructure that other engineers depend on.

Role DV Engineer · 10xEngineers

Focus UCIe Protocol VIP

Advocate RISC-V International

Ambassador CHERI Alliance

Tape-out Google MPW6 · Skywater PDK

Based in Karachi, PK · UTC+5

CHISEL HDL RISC-V ISA UCIe Protocol FPGA / ASIC Verification IP Chipyard CHERI Security Open EDA

View Projects → About Me ✉ Email GitHub ↗

3⁺

Years in RISC-V
ecosystem

1

Silicon tape-out
Google MPW6

6⁺

Conference papers
& talks

10⁺

Open source
projects shipped

About

Building open hardware,
one chip at a time.

The story of a software engineering graduate who got obsessed with what's underneath — and never looked back.

Profile

I'm Shahzaib Kashif — a CPU Design Engineer and Design Verification Engineer based in Karachi, Pakistan. My journey started with a question most software engineers never ask: what actually happens when code runs on a chip? That question pulled me into RISC-V, CHISEL HDL, and the world of open-source hardware — and I've never stopped digging deeper.

Right now I'm at 10xEngineers, building Verification IP for the Universal Chiplet Interconnect Express (UCIe) Protocol — one of the hottest emerging standards in the chiplet-based SoC space. I'm also an Ambassador for the CHERI Alliance, working to bring capability-based memory safety to new ISAs and toolchains.

"Hardware design should feel as iterative and open as software. I'm spending my career making that true."

As a certified RISC-V Advocate through RISC-V International, I spend real time on community — co-hosting meetups in Karachi, delivering workshops, mentoring students through LFX programs, and speaking at international conferences in Europe and North America.

My defining project: building a full SoC Generator in CHISEL HDL at MERL — which culminated in an actual silicon tape-out on Google's MPW6 shuttle using the Skywater 130nm PDK. Going from RTL to GDS to a real chip is an experience that permanently changes how you think about hardware. Every engineer should do it at least once.

I believe the future of chip design is open, software-defined, and community-driven. I'm doing something about it every day.

Experience

Design Verification Engineer

10xEngineers · Lahore, PK

Oct 2025 – Present

Active

Building Verification IP for UCIe Protocol — one of the most critical emerging chiplet interconnect standards
Developed comprehensive Verification Plan (VP) from UCIe Protocol Specification covering all compliance scenarios

Ambassador

CHERI Alliance · Remote

May 2025 – Present

Active

Promoting capability-based security through community outreach, workshops, and educational initiatives globally
Working with Special Interest Groups to port CHERI technology to new ISAs and existing toolchains

RISC-V Advocate

RISC-V International · Remote

Jan 2024 – Present

Active

Certified RISC-V Advocate — officially recognized by RISC-V International for community contributions
Co-hosted the RISC-V Karachi Meetup (2023) and CAMP-V Workshop
Mentored students through LFX Mentorship programs in RISC-V ecosystem projects
Regular speaker at RISC-V summits globally, representing Karachi's open hardware community

CPU Design Engineer

Intensivate · Berkeley, CA (Remote)

Oct 2022 – Jan 2025

Connected PCIe IP with CHISEL-based SoC Generator using Diplomacy and Cake Pattern
Designed and integrated RV-compatible Debug Module — made it work end-to-end with GDB in simulation
Wrote bare-metal testing firmware and CocoTB testbenches for design verification
Assisted with RTL and Gate-level simulations across the design flow

Research Associate

MERL · Karachi, PK

Nov 2022 – Present

Designed a full SoC Generator in CHISEL HDL — from bus interconnects to core integration
Taped out a generated SoC on Google MPW6 Shuttle using open-source Skywater PDK
Reverse engineered Rocket Chip — created the MASS (Micro Architecture & Software Spec) document
Extended Chipyard with custom MMIO Accelerators, RoCC Coprocessors, and novel cores via Cake Pattern
Prototyped Rocket Core on Arty-100T FPGA; ran AI workloads on Rocket+Gemmini SoC
GSoC '23 contributor — improved and validated LiveHD's power modeling flow
LFX Mentorship '23 — implemented TileLink UH in the Caravan Framework

Projects

Things I've actually built.

From real silicon tape-outs to cloud FPGA platforms. Click any project to see the full story.

Featured Project

SoC Studio

Full-stack web application for visually configuring and generating custom System-on-Chips. Features a drag-and-drop design interface, Chipyard-based RTL generation, real-time cloud simulation with waveform viewing, console I/O streaming, and on-chip AI inferencing modules — all in the browser.

CHISELReactDjango ChipyardFPGAAI/ML

Live Site ↗ GitHub

Full

Stack · RTL to Browser

Cloud

Simulation with Waveforms

AI

Inferencing in Simulation

01

SoC-Now

Open-source RISC-V SoC Generator with plug-and-play components. Started as my Final Year Project — became a published paper at WOSET 2022.

CHISELRISC-VFPGAWishboneTilelink

Designed generic, plug-and-play SoC components: buses (Wishbone, TileLink), devices (GPIO, UART, SPI, I2C, Timer), and a custom RV32-imfc core. Every parameter inside the generator is configurable via CHISEL's type system. Added a web interface on top to automate the SoC generation process and automated the entire FPGA mapping and bitstream generation pipeline.

GitHub Poster

02

NOVA — Cloud FPGA Platform

Emulating multiple RTL designs on AWS-FPGA F1 instances via PCIe runtime drivers. Full OS boot on a RISC-V SoC running entirely in the cloud.

AWS FPGAPCIeZephyr RTOSLinux Drivers

Wrote runtime drivers communicating with F1 instances through PCIe. Configured Zephyr RTOS for the custom RISC-V SoC. Wrote Linux Kernel Device Drivers to boot the OS by writing data into DDR — fully cloud-hosted. Also toggled FPGA hardware state (buttons, switches, LEDs) remotely from the cloud.

GitHub Website

03

Google MPW6 Silicon Tape-out

Actual silicon. Generated a full SoC using MERL's in-house generator, then taped it out on Google's MPW6 shuttle using the open-source Skywater 130nm PDK.

OpenLaneSkywater PDKASICGoogle MPW

Full ASIC flow: RTL → synthesis → place-and-route → GDS → submission via Google's Open MPW program. Used the Skywater 130nm PDK and OpenLane toolchain end-to-end. This tape-out validated the entire open-source hardware design methodology and proved the generator's output was genuinely manufacturable silicon.

04

Bitstream Chef

EDA tool for rapid FPGA bitstream generation via a graphical UI, backed by the F4PGA (Symbiflow) open-source toolchain. Published at WOSET 2022.

EDAF4PGAFPGAGUI

Designed to make open-source FPGA toolchains accessible to engineers who don't want to write config files. Graphical UI for constraint definition backed by F4PGA (formerly Symbiflow) synthesis flow. Published as a poster paper at WOSET Workshop 2022 alongside SoC-Now.

GitHub Poster

05

TileLink UH in Caravan — LFX Mentorship '23

LFX Mentorship under RISC-V International. Implemented TileLink Uncached Heavyweight in the Caravan SoC framework for plug-and-play bus connectivity.

TileLinkCaravanRISC-VLFXCHISEL

Extended Caravan with TileLink UH support alongside existing Wishbone and TL-UL support. Wrote a detailed blog post on RISC-V International's website documenting the implementation journey and design decisions.

GitHub Blog

06

LiveHD Power Modeling — GSoC '23

Google Summer of Code 2023 contribution: improving and validating the power modeling flow of the LiveHD hardware design framework.

GSoCLiveHDPower AnalysisEDAC++

Improved stability, accuracy, and compatibility of LiveHD's power estimation system. Established a thorough validation methodology against known ground truths. Optimized the flow for larger netlists and VCD files, fixing edge cases causing incorrect power readings in hierarchical designs.

GSoC Page

07

Reverse Engineering Rocket-Chip

Applied software engineering documentation methodologies to UC Berkeley's Rocket Chip Generator. Presented as a tutorial at RISC-V Summit North America 2020.

Rocket-ChipRISC-VArchitecture Docs

Created flowcharts, class diagrams, and block-level architecture diagrams for the Rocket Chip generator. Produced a "Micro Architecture and Software Specification (MASS)" document covering core-level specifications. Presented at RISC-V Summit 2020 — an early milestone that sparked a lifelong journey in community advocacy.

Recording Slides

Blog

Writing about things that matter.

Open hardware, RISC-V ecosystem, community building, and honest lessons from shipping real silicon.

Pinned · Most Read

What I Learned Taping Out My First Chip (and Why You Should Do It Too)

The Google MPW6 shuttle experience — from a casual "we should tape out a chip" to actually holding a GDS file that got sent to a fab. Every mistake, every 3am debugging session, every time I thought the flow was broken. The full unfiltered story of MERL's first real silicon, and what open-source ASIC flows actually feel like from the inside.

RISC-VOpenLaneSkywater PDK12 min read

Read on Site ↗

Jun 2023

LFX Mentorship

Integrating TileLink UH in the Caravan Framework

A deep technical walkthrough of implementing TileLink Uncached Heavyweight in an open-source SoC framework. Bus protocol internals, CHISEL Diplomacy patterns, and what the process taught me about hardware abstraction layers.

Read on RISC-V →

Jun 2023

LFX Mentorship

Adding Floating Point to a RISC-V Core in CHISEL

Implementing the F-extension in NucleusRV. The tricky parts of FPU design, how the RISC-V spec handles edge cases, and how we plugged the whole thing into the SoC-Now generator to expand its capabilities.

Read on RISC-V →

Sep 2023

Community

RISC-V Karachi Meetup — Building Open Hardware Community from Scratch

We co-hosted the first RISC-V meetup in Karachi. Here's what we learned about running technical meetups, engaging students with open hardware, and why Pakistan's engineering community is more than ready for RISC-V.

LinkedIn Post →

May 2023

Conferences

ChipShop: What Presenting at RISC-V Summit Europe 2023 Felt Like

A reflection on presenting at RISC-V Summit Europe in Barcelona. The energy of the RISC-V ecosystem, conversations with chip designers from across the globe, and what the future of SoC design tooling looks like from the inside.

View Abstract →

Oct 2022

Architecture

Reverse Engineering Rocket-Chip: A Software Engineer's Approach

What happens when you apply software engineering documentation techniques — UML, flowcharts, class diagrams — to a 100,000-line Scala hardware generator? The story behind my RISC-V Summit 2020 tutorial.

Watch Talk →

→ More articles in progress. Follow @shahzaib_kash for updates.

Publications & Talks

On the record, in the room.

Papers, posters, and talks at international venues — from Karachi meetups to ASPLOS workshops in Europe.

6

Conference
Contributions

4

Published Papers
& Posters

3

Continents
Represented

5+

Years Speaking
Publicly

Papers & Posters

'23

RISC-V Summit Europe · Extended Abstract & Poster

ChipShop: A Cloud-Based GUI for Accelerating SoC Design

Shahzaib Kashif, Talha Ahmed, Mahnoor Ismail

Source Certificate

'23

First FireSim & Chipyard Workshop · ASPLOS 2023

ChipShop: A Cloud-Based GUI for Accelerating SoC Design

Shahzaib Kashif, Talha Ahmed, Mahnoor Ismail

Slides Video Program

'22

WOSET Workshop (co-located ICCAD 2022) · Poster

SoC-Now: An Open-Source Web-Based RISC-V SoC Generator

Shahzaib Kashif, Talha Ahmed, Muhammad Shahzaib, Dr. Farhan Ahmed Karim, Hadir Khan, Usman Zain

Code Poster Slides Video

'22

WOSET Workshop (co-located ICCAD 2022) · Poster

Bitstream Chef

Shahzaib Kashif, Talha Ahmed, Dr. Farhan Ahmed Karim

Poster Slides Video

Talks & Workshops

RISC-V Summit North America 2020

Reverse Engineering of Rocket-Chip

2020 · Tutorial Session

Recording Slides Tutorial

RISC-V Karachi Meetup

Co-Host & Technical Speaker

September 2023 · Karachi, Pakistan

Co-Host

CAMP-V Workshop

RISC-V Architecture & Ecosystem

2023 · Organizer, Host & Speaker

Organizer

Certifications

⚡

RISC-V Foundational Associate (RVFA)

RISC-V International & Linux Foundation

📡

RISC-V Advocate

RISC-V International

📘

RISC-V Fundamentals (LFD210)

Linux Foundation

🎤

RISC-V Summit Europe 2023 — Poster Presenter

RISC-V International

🧑‍🏫

RISC-V Project Mentorship (Mentee)

RISC-V International / LFX

☀️

Google Summer of Code 2023

Google / LiveHD Project

Contact

Let's build something meaningful.

Whether it's open hardware, a RISC-V project, a speaking opportunity, or just a good conversation about chips.

I'm always open to conversations about open-source hardware, verification engineering, RISC-V tooling, and community building in the hardware space. If you're working on something interesting — a chip startup, a research project, an educational initiative — let's talk.

Based in Karachi, Pakistan, working fully remote. Available for consulting, speaking engagements, and collaborative projects anywhere in the world.

✉ Email shahzaibceo@gmail.com ⌥ GitHub github.com/shahzaibk23 in LinkedIn shahzaib-kashif-2655a1178 𝕏 Twitter @shahzaib_kash ⊕ Portfolio shahzaibkashif.netlify.app

Currently open for

Full-time or contract roles

Open hardware collaborations

Speaking & workshop engagements

Mentorship opportunities

RISC-V ecosystem projects

Research collaborations

Response time

Usually < 24 hours

Timezone

PKT · UTC+5

Preferred

Email / LinkedIn

Mode

Remote anywhere

Shahzaib Kashif.

Building open hardware,one chip at a time.

Things I've actually built.

Writing about things that matter.

On the record, in the room.

Let's build something meaningful.

Shahzaib
Kashif.

Building open hardware,
one chip at a time.